Nibbler 4 Bit CPU(bigmessowires.com) |
Nibbler 4 Bit CPU(bigmessowires.com) |
Wow!
[] Indirect addressing was an optional feature on the IBM 1401 for an additional monthly fee.
On the topic of processors made from 74xx TTL, I'll point out the Datapoint 2200 desktop computer. This had a board of TTL chips equivalent to the 8008 microprocessor. The 8008 was actually designed to replace this TTL-based processor. Trivia: the x86 is little-endian because when building a serial computer from TTL it's easier to use little-endian. https://en.wikipedia.org/wiki/Datapoint_2200
The Nibbler is different from the PDP, Datapoint, etc in that the Nibbler has very, very few chips; almost all the logic is done in microcode. This is the same trick used to build a "single-chip" processor from the Four Phase AL1. https://en.wikipedia.org/wiki/Four-Phase_Systems
And still it runs with 1MHz, the same speed of my first computer ;) with a dedicated integrated CPU.
I guess, the PDP has at least 10 times more (equivalent) chips inside.
M8310 - 53 chips (http://www.classiccmp.org/hp/My%20PDP-8%20Cards/M8310.jpg)
M8300 - 64 chips (http://www.classiccmp.org/hp/My%20PDP-8%20Cards/M8300.jpg)
So 117 chips, so not quite 10X but the nibbler does have an LCD display and if you add the PDP-8/e programmer console to the mix you're probably close to 170 chips. So great estimate!
I think, you can not give this design a negative, because it is much simpler than early microprocessors.
I forgot about the ROM, and apologize for it.
(Meanwhile, current Intel processors have 2 MiB microcode files.)
1: https://fsf.org/blogs/community/active-management-technology
No, it doesn't; neither from a practical, nor from a theoretical point of view. Theoretically, ROMs are equivalent to the class of pure, total, mathematical functions (i.e., each input value maps to exactly one output value), while FPGAs are equivalent to the class of deterministic finite automata, because they contain internal state.
> After all, an FPGA is just a load of units of small ROM areas, with the inputs and outputs linked to each other.
You're forgetting the memory elements – they're crucial to the functionality of FPGAs.
I'd argue that an even more critical feature of FPGAs is configurable routing. ROMs don't have that either. :)
Actually, now I wonder whether it'd be possible to build memory out of ROM by looping outputs back to inputs...
You actually don't need configurable (programmable) routing: We can model every synchronous circuit as a Mealy machine [1], therefore we need two functions and a register. Every function can be constructed from a hierarchy of programmable, fixed-size LUTs which are statically connected (for example, you can build a 5-input LUT from three 4-input LUTs). Now you don't need to build routing, it's implicit in the next-state and output functions.
[1] like this: http://electrosofts.com/verilog/mealy.gif