SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series(cnx-software.com) |
SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series(cnx-software.com) |
"What are the goals of the project? To create a fully open SoC and low-cost development board and to support the open-source hardware community. This will involve volume silicon manufacture..."
They have 2 folks with prior experience on the Rpi team. But, it's hard to tell when they might have something ready. http://lowrisc.org
The upshot of this is you can run lowRISC 0.6 on something like the Nexys 4 DDR (other FPGAs are available) and have a real Linux distro running on an FPGA, rather slowly and with limited RAM. They even managed to make the ethernet port work using an entirely free stack (though you still unfortunately need Vivado for a while to compile it) and it's a step towards having an ASIC that is completely freely licensed. So it's still baby-steps but I'm glad the lowRISC project came back to life.
Something they can fix, but this iteration's going to be not very convenient because of that.
The HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310 making it the best way to start prototyping and developing your RISC‑V applications. Not only can the HiFive1 help build RISC-V platforms, but it is also the first commercially available option to do so! The HiFive1 can simply be plugged into your computer via the micro USB port located to the front of the board. Additionally, the HiFive1 comes programmed with a simple bootloader and a demo software, that way you aren’t restricted to the Arduino IDE if you don’t choose to do so.
But after learning about how small the RISC-V instruction set is (less than 50 apparently, but I can't find a citation for that anywhere), I'm far more motivated to get into it.
My only experience porting node was to a specialized ARM system a while ago, so ARM support may have been already built in or things may have changed.
edit: as people have commented, there indeed is a fair amount of arch specific stuff for reference the mips directory https://github.com/v8/v8/tree/master/src/mips64
https://docs.google.com/presentation/d/1_eLlVzcj94_G4r9j9d_L...
What would be the use case for a 320 MHz processor with 16 KiB RAM? Even ESP8266 has 80 KiB and runs at 80 MHz.
That said, whether you choose to start with it or RISC-V, from personal experience SiFive's implementations are phenomenal. I used one of their free-implementations, and I was blown away by how easy it was to use their automated tools to build a core exactly the way I wanted. Not as easy as generating a NIOS core, but much more capable. With an Artix-7, I had a very capable low-range processor in about an hour.
https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...
from the times when x86 wasn't that big: http://pastraiser.com/cpu/i8080/i8080_opcodes.html
30 years ago we were typing the hex codes of those commands straight into the Forth words bodies using the mental copy of that table (as you see it has very logical easy to remember organization)
Assuming it's priced comparably cheaper to the raptor, I am buying a blackbird as soon as it comes out.
Also there's the SoftIron Overdrive 1000 (sold only as full system, not bare board)