Computers without clocks (2002) [pdf](cs.virginia.edu) |
Computers without clocks (2002) [pdf](cs.virginia.edu) |
First, here are various search terms: clockless, self-timed, delay-insensitive, latency-insensitive, quasi delay-insensitive (QDI), speed independent, asynchronous, bundled-data
There are a wide variety of clockless circuits that each make their own timing assumptions. QDI is the most paranoid, making the fewest timing assumptions. Bundled-data is the least paranoid (its effectively clock-gating).
A clockless pipeline is always going to be slower than a clocked one and requires about 2x the area. However, clockless logic is way more flexible, letting you avoid unnecessary computation. Overall, this can mean significantly higher throughput and lower energy, but getting those benefits requires very careful design and completely different computer architectures.
Most of the VLSI industry is woefully uneducated in clockless circuit design and the tools are terribly lacking. I've seen many projects go by that make a synchronous architecture clockless, and they have always resulted in worse performance.
What this means is that it would take billions of dollars for current VLSI companies to retool, and doing so would only give them a one-time benefit. So, you probably won't see clockless processors from any of the big-name companies any time soon. What they seem to be doing right now is buying asynchronous start-ups and shutting them down.
As of the 90nm technology node, its not possible to be switching all of the transistors on chip without lighting a fire. This mean that the 2x area requirement is not much of a problem since a well-designed clockless circuit only needs to switch 25-50% of them at any given time. Also since 90nm, switching frequencies seem to have plateaued with a max of around 10 GHz and typical at around 3 GHz. When minimally sized, simple clockless pipelines (WCHB) can get at most 4 GHz and more complex logic tends to get around 2 GHz (for 28nm technology). Leakage current has become more of a problem, but it's a problem for everyone.
There is a horribly dense wikipedia page on QDI, but it has links to a bunch of other resources if you are curious.
How come? In a clocked design, you have to have clocks slow enough so all possible logic paths would finish. In a clockless one the propagation only takes as much as needed, and in a case of shorter path can take less time, doesn't it?
Also, the speed of a linear pipeline is limited to the slowest stage in the pipeline whether or not you use clockless. Clockless only helps pipeline speed when you have a complex network.
I do see some high speed low power networking hardware moving this way: Router Using Quasi-Delay-Insensitive Asynchronous Design
There's a plan!
https://www.nedbingham.com/intel_max_transistor.png
https://www.nedbingham.com/intel_switching_frequency.png
What effect will this have on our programming languages and programming idioms? To some extent, our low-level programming languages have influenced CPU design, and vice versa, but it's not clear what effect an architectural change like this would have.
Though all of this is assuming we solve the memory bottleneck... which... might come about with upcoming work on 3D integration and memristors? who knows.
About 1/3 to 1/2 the power usage is leakage and I don't see how a clockless design will help that. We dynamically lower the voltage and have power islands for unused or lesser used portions.
nbingham makes a great point about the tools. We have invested billions of dollars in tool flows. We are not going to throw that away until we see some proof that clockless designs are better in some measurable ways.
Yeah, async design takes a while, and async chips don't tend to be well advertised, but they are there.
Async FPGA has 60% less power, 70% increased throughput http://csl.yale.edu/~rajit/ps/fpga2p.pdf
High speed routing (from Fulcrum, one of the startups bought by Intel and shut down) https://www.hotchips.org/wp-content/uploads/hc_archives/hc15...
Ultra low power processor https://ieeexplore.ieee.org/abstract/document/1402056/
Ultra low power neural network accelerator from IBM https://www-03.ibm.com/press/us/en/pressrelease/44529.wss
I haven’t seen any legitimate uses for it yet, but it’s very cool.
Strange Loop 2013 presentation: https://www.infoq.com/presentations/power-144-chip
[1] https://news.ycombinator.com/item?id=11425533
[2] https://news.ycombinator.com/item?id=11426825
[3] https://web.archive.org/web/20120227072220/http://fleet.cs.b...
You're right, and I don't intend to condemn all of async, or even QDI for that matter :) I am doing my PhD on it, so I do think there is promise. I just think that arithmetic is better handled by Bundled-data specifically. Let QDI do the control leg-work and tack high-performance arithmetic to it.
Also, Gasp is certainly faster, but is limited to simple pipelines. That's why I like QDI, it lets me make weird circuits.
EDIT: Sorry, I got mixed up between the conversation threads... dislexia is a thing.
I'm not saying condemn async or QDI, but we must recognize what it is good at and what it is not. A QDI pipeline stage may be slower, yes. So don't use it if you just want to implement a linear pipeline. But do use it if you have a complex network because of the previously mentioned benefits. Gasp and other async pipeline topologies don't have the flexibility of QDI, and there isn't really a good framework to mix them with QDI techniques at the moment (maybe relative timing?). The power of async comes from this flexibility and the ability to avoid unnecessary computation.
Bundled data is a simple control with data clocked from that control. Its very much keeping arithmetic away from the QDI circuitry.
Though to be fair, I haven't seen a good examination of how pass transistor logic might affect QDI arithmetic circuitry, so maybe there is hope.
Did you check if they're FPT? (Fixed Parameter Tractable)
