The “terrible” 3 cent MCU – a short survey of sub $0.10 microcontrollers(cpldcpu.wordpress.com) |
The “terrible” 3 cent MCU – a short survey of sub $0.10 microcontrollers(cpldcpu.wordpress.com) |
A friend who frequently does contract development in the toy space has (or at least used to have) a favorite go-to MCU that costs under $0.06 in bare die. It is essentially a 6502 with 100 bytes of RAM and a metric butt-load of mask-programmable ROM. It was originally designed for greeting cards. He has designed it into toys.
It is hard to use, you need a dev kit and a good relationship with the distributor to get the documentation. It only makes sense in high-volume products, since it comes as passivated bare die so assembly requires a die-bonder and expoxy encapsulation depositer.
Not for everyday use. But as my friend says: “You haven’t lived until you have spent an entire afternoon arguing over $0.05 on the BOM.”
Edit: Oops. I conflated projects. The toy project actually used a SunPlus MCU, not a Winbond MCU. It was an 8-bit RISC CPU running at 5MHz with 128 bytes RAM and 256KB mask ROM. The ROM held both the program and audio samples. I don't recall what encoding was used for the audio.
http://www.embeddedinsights.com/channels/2010/12/10/consider...
http://www.ganssle.com/rants/is4bitsdead.htm
The two examples were timepiece designs and Gilette Fusion ProGlide. On top of getting yours, I'm curious if any of these cheap MCU's in the article could today have met whatever your requirements were for a 4-bitter?
In Brazil, Holtek has a huge presence in that niche.
Without question, one of the nicest platforms to have in multitudes of thousands, at low energy and cost ..
What would that be in this context? I'm guessing we're talking KB rather than TB?
1 MB would be enough for 45 seconds audio at 8 bit PCM @22 kHz. If they're half competent, they could use ADPCM or much better (and cheaper to decode too!) vector quantization.
With VQ, you could go even down to ~1 bits (~6 minutes of audio per megabyte) per sample while maintaining good audio quality. Decoding is very simple, so 6502 would have plenty of oomph to do that.
I think a fascinating experiment here would be to invest some time in an unencumbered scalable design that could be implemented very inexpensively (say less than 10K gates). Would these manufacturers pick up that design and run with it, making variants and parts that people could buy? It would get Microchip off their back (several have been sued apparently).
Today, Mouser lists 1 pcs @ € 0,908, 100 pcs @ € 0,863.
The guilder/€ is 2,20371 ( muscle memory ).
The MCUs in the article are 12C508A class, one is an actual clone.
So for ~ € 0,80 at quantity, the 12C508A currently costs about 1.75 guilder. 20 years later.
I did a Digikey comparison once, and Microchip alone provided roughly 30% of all MCUs on digikey. It has, for example, an incredible 175 MCU models with exactly 64B of RAM, 1.75KB of ROM and just 5 I/Os.
* Two voltage options (although why on earth do they need 2-5.5 and 2-5 separately?)
* Two main packaging options: tape and tube, and tape is furthermore available as full reel, digireel, and cut tape
* Three different temperature ratings
* Five different device packages from tiny 3x3mm DFN to full-sized DIP
So already from these fairly simple options you get total of 2x4x3x5 = 120 different combinations for essentially the same chip. So they don't quite have all the combinations, but there are few outlier options and overall the combination coverage is pretty wide which explains the inflated SKU count. I'm not sure what conclusions can be drawn from this exercise besides that Microchip seem to be willing to provide their chips exactly as customer wants them.
If you're allergic to 555s, I guess?
Popularity of the 555 waned a long, long time ago.
(In single quantities from LCSC the cheapest 555 is $0.07 and the cheapest Paduak microcontroller is $0.04 - in quantity the 555 is $0.04 and the Paduak is $0.025. Plus fewer support passives with the Paduak.)
hmm. Well I don't blame the author but that kinda killed my interest
My hardware guy came on really heavy against the Padauk stuff because it was put to me that the temperature range wasn't wide enough particularly at the high end where supposedly we had to operate at 125C. I actually think attinys made it in the design instead of the Padauks just because of personal preference and an unwillingness to share the project rather than unavailability in automotive temp range.
So the tubes of Padauks and a pair of ICEs I brought in so it would be very easy to play with sit unused and I am now at a different place that places more emphasis on what all of the engineers think rather than just whoever happened to draw the long straw for the project.
It was a fun little project: http://www.dadhacker.com/blog/?p=1911
I still remember a friend relating with a mixture of horror and fondness that in 15 years probably the biggest impact he ever had to the bottom line of [big computer manufacturer no longer in existence] was re-routing a PCB in a way that let them make it smaller with no functional change. The materials cost savings over product lifetime was in the 7-8 figures range, he claimed.
http://www.righto.com/2016/09/sonicare-toothbrush-teardown.h...
https://www.emmicroelectronic.com/catalog?title=&term_node_t...
EM Microelectronics is actually not so obscure. They belong to the Swatch group and are specialized in ultra lower power analog and mixed signal circuit. Obviously, first for watches.
And I buy the heads from Asia too for a fraction of the store price.
I buy cloned heads (but not the main brushes) and find them completely adequate.
I have done that thought experiment many times. I have a ISA that I sketched out many years ago but never did anything with. Often, I have thought it would be a real hoot to put up a working Verilog model on Github with a public domain license just to see if I could bait somebody in China into manufacturing it for me so that I could buy it off Digi-Key :)
Of course, the CPU isn't really the value any more. One salesman for an ARM licensee said it best: "Look at the die photos from any of the ARM licensee's. We are all just selling value-added flash." And as far as that goes, it isn't the CPU that drives the part design-in decision. It is having good, bug-free, peripherals in the right mix and a reasonable tool chain.
So the "free CPU design as wild oats" idea has appeal, but it would need an LLVM back-end to go with it, at minimum, and then unencumbered Verilog for a collection of basic peripherals.
WCH, which sells cheap mcu's(like $0.25 8051-mcu with usb/16Kflash) is working on a risc-V bluetooth mcu:
https://www.cnx-software.com/2019/02/16/wch-ch572-risc-v-mcu...
And since risc-v has versions somewhere around 5K-10K gates, well, a lower end mcu isn't far, probably.
Still, it would be interesting to think how we can get from that, to standard peripherals, and standard pinouts, used by at least 2 mcu makers. That would be interesting.
5-10k? Seriously? That's amazing.
Z80 had 8500. According to Wikipedia, even truly simple and bare bones 6502 had 3510 or 3218.
Just implement bank switching for top 32 kB of address space. 256 banks (= one 8-bit register) * 32 kB = 8 MB. Need more? Add another bank switch register and you got up to 2 GB.
It should be faster, and could be if I reworked it. But I'm mostly using the arduino as a crutch right now until I get hooked up to real driving circuitry so I'm not overly concerned.
The ALU can be a reasonable chunk of the processor size, and an 8-bit ALU is going to be much smaller than a RISCV ALU. Although I read somewhere that some of the Z80s, although an 8-bit processor, had a 4-bit ALU, and also I read somewhere that the 32-bit NIOS processor has a 16-bit ALU. But whether that's true or not ...
I designed a size optimised 16-bit MSP430 clone for small size low cost machxo3 FPGAs that used an 8-bit ALU. It a good way of keeping the number of LUTs down when optimising for size over speed.
For something like the low cost ice40 FPGAs, a PIC would probably be a very good match for those too compared to RISCV, because ice40 doesn't have distributed memory, which is what you'd like for register files (otherwise I expect one of the block RAMs would be used for the register file, and ideally you wouldn't want that to happen).
Agreed, they work fine.
Could you write a guide? I would buy it.
A big part of how I'm today is due to my boss at that time. One of the most brilliant engineers I worked it. He also gave us a lot of time and freedom to think of these kind of approaches. Sadly these days a lot of companies are always in a rush so one can't think things through properly.
Makes sense.
Do you have an encoder/decoder to point us to?
There's some decoder code there as well.
The older nodes don't seem obsolete if component reliability is a concern. All my concepts consider their potential. They're quite limited in performance, storage size, and energy, though. There's a tradeoff. Lots of companies want a cheap, reliable, simple CPU/MCU. That's where the oldest nodes shine. That said, the newest nodes are tiny enough that one might make a 2 out of 3 setup with extra error correction like Rockwell-Collins' AAMP7G CPU. Might still be pretty cheap... per unit (not development cost)... on 28nm CMOS or SOI process. Haven't seen an attempt.
Do you have funding to do a MOSIS run or two? I wonder if we could find some.
If you do a project, I suggest 350nm since it's the last node that you can visually inspect the resulting silicon. It's as fast as you go before you need electron microscopes and such. It's also more likely that the open tools for hardware will be able to handle such a node instead of deep sub-micron. Finally, there's old research in transistor-level optimization that might be applied to it in new, open tooling. Might let people do standard cell that inches a bit closer to performance and energy use of custom designs.
1/6 of a penny is 0.0016 USD, or 0.01 CNY: https://www.google.com/search?q=0.0016+usd+to+cny
The CMOS rule of thumb is one gate is 4 transistors (eg a 2-input NAND). But the first Z80 was nmos, and so the equivalent count is harder to state. 3 transistors per 2 input nmos gate is a rough first order guess, but in nmos wide gates still need only a single load resistor, and designers sometimes used dynamic logic to save even more transistors.
I stand corrected.
These were more commonly used back when transistors were expensive.
(https://news.ycombinator.com/item?id=20688443 is on the same topic.)
(As others commented, those are transistor counts.)
~1000 Luts. 1 Lut = 6-24 gates on average. a bit pmore but still pretty close.
FPGAs have things like block RAMs and multipliers. Those require a ton of gates, but don't increase required FPGA LUT count by much.