Intel Reinvents Transistors Using New 3-D Structure(newsroom.intel.com) |
Intel Reinvents Transistors Using New 3-D Structure(newsroom.intel.com) |
http://www.anandtech.com/show/4313/intel-announces-first-22n...
[1] Wider transistors also cause more capacitance for the other transistors that are driving them, but for most modern designs this is smaller than line capacitance.
[2] Having transistors closer together can also help overcome speed-of-light delay. This can be important in caches.
EDIT: Also, some stuff I didn't notice until reading the Anandtech article is that the thinness of the silicon will give you the same artificial limitation of the depletion region that SOI does, leading to the same accelerated inversion. Oh, and better isolation from the base too. I don't think that I can explain that succinctly for non-EEs so go read Wikipedia on MOSFETs if you're interested.
But in this case, while they take up less space, the distance is the same -- they're simply traveling up and over, rather than just over. Unless I'm missing something here.
I'm not sure what the electrical propagation speed is in modern ICs, but let's assume its about 1mm per pico-second (3 times that of vacuum). So for each mm we move our cache elements closer we gain 2 ps in round-trip delay. On a 3GHz processor you've got 333 ps per cycle, the i5 die is about 13mm across, going from 32 to 22nm process might shave as much as 3 or 4mm of the longest path. Giving a 6 to 8ps gain, potentially a 2% improvement. Interesting.
In a nutshell, the drain/source is a tall trace, the gate approaches from the side and climbs over the drain/source, covering it on three sides.
It is as you said - instead of the gate controlling the flow in a shallow ditch (the old "2D" does have some depth ;-), they built up a pipe and the gate is the choke around it.
Well, that should help stem the pesky leakage current problems that plague the deep sub-micron technologies ...
The article links to some graphics: http://www.nytimes.com/imagepages/2011/05/05/science/05chip_...
I'm a sucker for videos. This Tri-Gate tech was first announced in 2002, I love seeing pie in the sky technology come into reality and widespread usage.
Intel will likely not patent or reveal the manufacturing method thats how most semiconductor manufacturing technologies go. They tend to be trade secrets that are a combination of process and machinery which your competitors are unlikely to ever reproduce exactly, so no point in patenting it.
Below 10nm, Intel and other fabricators will start looking beyond CMOS, perhaps to carbon based structures.
When Intel was at 45, the ARM makers were 65. Intel at 32, ARM makers at 40/45.
When Intel will be at 22. ARM makers will be at 28/32. When they'll be at 10nm, ARM will be at 14nm using IBM's foundry.
Thats how transistors work in general, but the problem is you get small enough and its like the transistors want to turn them-selfs on, luckily the smaller you go the more leakage you get into other areas of the chip so those extra electrons just get seeped into there and ground out which mostly causes you to pull more power per square area.
You real issue is if those "jumping" electrons get wedged into corners near gates, then they can leave a transistor on permanently. But that's all part of the chip design process to avoid that kind of thing.
"The key to today's breakthrough is Intel's ability to deploy its novel 3-D Tri-Gate transistor design into high-volume manufacturing."
"The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel's 32nm planar transistors."
Really, Moore's law is a sort of management principle rather than any kind of physical law. Simply, Intel introduces new fabrication process technology at the pace which optimises their profits.
Advance too slow and competitors will take the business, advance too fast and capital costs are higher, plus customers need payback on their current purchases. Advance at just the right pace and customers are motivated to replace perfectly good products just a few years old.
See 2007 for a similar announcement and reaction:
http://hardware.slashdot.org/story/07/01/27/1614207/Intel-IB...
I wonder if this is truly Intel's invention or not:
It's also worth pointing out that current Atoms in the market are still 45nm parts, not even 32nm. Intel, for obvious reasons, tends to prioritize production of high-margin desktop and server CPUs over low-margin embedded parts.
Really, this announcement isn't about ARM-based vs. Intel-based SoC designs. I think it's clear that Intel has some catching up to do there. This is about Intel cementing and extending its complete and total dominance of high end digital logic fabrication. At this point they look to be about a full two years ahead of everyone else. AMD, IBM, Samsung, TI, TSMC and the rest of that crew have to be more than a little worried.
Objectivity disclaimer: my wife is at Intel working on precisely this 22nm process. So I'm about as biased a source as you can find.
Given that, (and given that Intel has been dominant in process technology for some time now) I've always wondered why Intel doesn't do fabrication for third party, high-performance/high-margin/high-power-budget products that don't directly compete with Intel's main CPU product line. Networking/telecom processors, top-end FPGAs, DSPs, and so forth. Is it just that they are at capacity making CPUs and don't see any need to get into that business? Or do they do it already and I'm just not aware?
...provided Intel grants the IP, know-how and equipment to its rival.
> dominance of high end digital logic fabrication
Disruptions typically begin at the low-end, with the disrupted incumbent earning great margins at the high-end - just before they get killed. Smartphones are the low-end. ARM is probably already too well established there for Intel to win it (with popular machines, OSs and applications dependent on ARM).
The danger to Intel is that as ARM improves in performance, it brings other benefits with it (eg. low power consumption; configurability), that are also valuable in high-end logic. Once ARM is performant enough, those server-farms could switch, to solve their heating/power problems.
But it's interesting that Intel hasn't made the low-end a priority, not applying their best process to it; maybe they have a reason to think they're safe.
Hardly the end of the world for ARM.
It would basically come down to whether Intel chose to embrace ARM, or tried to use the new position to quietly strangle it.
"TRI-GATE DEVICE WITH CONFORMAL PVD WORKFUNCTION METAL ON ITS THREE-DIMENSIONAL BODY AND FABRICATION METHOD THEREOF"
Plus, there's far from a consensus that this is the best design out there. It hasn't been proven in mass production yet. STMicroelectronics, a massive player in microcontrollers (which often go into applications with even tougher power constraints than mobile phones), is pushing Silicon on Insulator pretty for their next generations.
As a result, 10nm will be released in 2015, rather than 2020 as ITRS predicted in much earlier roadmaps.
What gets real interesting in just a few years is how Intel and others will get below 10nm. Could be a shift to carbon based structures will be necessary.
If Intel had found a way of making signals propagate three times faster than the speed of light in vacuum, everyone would be too busy rewriting the laws of physics to take notice of their transistor technology improvements.
A 3mm path-length difference would be more like 10ps; 20ps for a 2x3mm round trip.
(But I bet Intel take a lot of trouble to reduce those distances. There probably isn't anything that has to happen in a single cycle that involves 6mm-worth of propagation delays.)
They can't switch the manufacturing process every year.
I've worked with audio equipment that uses FPGAs, CPLDs, and DSPs for various purposes, and being stuck on relatively-ancient processes makes that equipment generate a lot more heat and fan noise than would be necessary with DSPs and FPGAs on a modern process.
It has been speculated in the financial press that Intel might try to offset its huge annual capital expenditures by offering as much as 20% of its fab capacity as foundry services.
I don't know if it's true five years later now, though.
We need pin outs and thermal conductivity - stacking layers of transistors is bad for both.