How a CPU works: Bare metal C on my RISC-V toy CPU(florian.noeding.com) |
How a CPU works: Bare metal C on my RISC-V toy CPU(florian.noeding.com) |
Like, emulate gates and keep building bigger pieces until you have a function that’s a CPU. Etc.
I guess I’m thinking a bit more lower level than an emulator where you implement an opcode using normal capabilities of your language of choice.
I guess TFA is pretty close to this in ways, too.
Much faster than Logisim, UI a little clunky, but my CPU runs around 0.5Mhz and it has very nice peripherals like Telnet, graphics ram, VGA etc
Terrible name that is hard to google, but great tool.
hardcover:
https://www.lulu.com/shop/gerg%C5%91-%C3%A9rdi/retrocomputin...
or digital:
Link: https://www.amazon.com/Code-Language-Computer-Hardware-Softw...
It's got a very slow, methodical onramp with a lot of diagrams and a light, breezy style. You end up building a (very simple) computer in the end, including instruction processing.
I recently came across https://makerchip.com/, and the TL-Verilog language it supports looks useful for when you want to make a pipelined design later.
In short, you can define generic reusable flow constructs like stall and backpressure pipelines. You can then instantiate them and slot in your logic, and signals will be automatically pulled through the different stages and pipelines as needed. The example at this part of the video shows then how adding something can be a two line change when it would be hundreds of lines if you were working at the RTL level: https://youtu.be/hQ6HhOBHKy0?t=2581
- WASM version: https://comparch.edu.cvut.cz/qtrvsim/app/
- source & native releases: https://github.com/cvut/qtrvsim
It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.
I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented:
Side note: the articles on compilation also seem to be good and simple to understand, especially the one about code generation (which is a topic that other articles somehow always skip)
[I think there's a minor typo in the Combinational Logic section - should it read "(sometimes also called combinatorial logic)"?]
I'll think about sharing the code. Large code parts - while working - did not pass my quality bar, since I did not have enough time to clean and refactor while learning. But maybe that's fine. Hmm.
Oh I think it's more than fine :)
Your goal wasn't to write a C++ or Python app it's was to create almost everything from first principles. I also don't think anyone would doubt your abilities after reading this post. You could link to the article in the repo. I think it's speaks for itself. My first thought when I read the article was "Wow, this is great." I've read it twice now. Thank you for sharing.
Oh, and what was done, it would be illegal with x86_64 and arm64 as you would have to pay a license in some countries... once you want to make money out of it.
Here's the repo: https://github.com/fnoeding/fpga-experiments
I'll update the post with it too.
Its like 95% measuring and cutting, 5% thinking, testing and debugging.
Its a bit of a welcome relief from software, which is 95% thinking and 5% typing. A bit of monotony might be good for the brain.