The F-16 back when I started my career at General Dynamics was slated to use implementations of Mil Std 1750A, with the Z8002 as an interim processor for the fighter's next generation computers (F-16C/D in the early/mid 80s). I wrote some of the Jovial runtime that was intended to be used for both processors. No idea what happened to that code since I left in 1984. The 1750A had a math coprocessor which made things a little easier than the Z8002.

I have so much moe for the various post-Z80 chips Zilog made that people think failed in the marketplace but are still around and perfectly viable for applications that don't need 32-bit

https://en.wikipedia.org/wiki/Zilog_eZ80

But the thing is that you keep getting dragged kicking and screaming to ARM because even if it is boring it is capable, affordable and everywhere.

From the wiki link of the z8000 there is a curious bit of Commodore history I never knew of: https://en.wikipedia.org/wiki/Commodore_900

C. had a pretty good deal with zilog, but they pissed it away for maybe not very good reasons....

Had things gone different C900 and the like might've been there instead of the Amiga.

I actually took the Captain Zilog self-study course (probably in 1981 or 1982). They mailed you the first installment and you answered the questions. Then you mailed back the answers to get graded and receive the next installment. I think the completion prize was a Captain Zilog t-shirt.

The thing that I remember was that the Z8000 had some pretty complex addressing modes.

There was an earlier, and to my way of thinking, much better idea at Zilog than the Z8000. That was the Z280 (later christened the Z800) it was a 16 bit machine akin to the 8086 but with upward compatibility with the Z80 and a much nicer architecture. I believe that Godbout made and S-100 card with this processor at one time. I wanted one so badly and yet the 8088 and the IBM-PC steamrolled the industry because "big blue" and all that. Sigh.

Very impressed, how obvious looking high level design flaws of Z8000. And these are not technical flaws, but sure C-level decision flaws.

Only one question decided it's fate - why SMALL startup decided to make CHEAP design?

- It was obvious, it was impossible to compete with Intel on large cheap market. But obviously, Intel would not compete on niches, where startup without legacy could make something significantly better!

Exxon as a foundation, is not good, because their money was not money of Faggin, even more than money of investors are not money of Intel execs.

So, second drawback, of Zilog's situation, that Faggin was far more limited in maneuver then Intel's tops. So why he even more limited himself with cheap design?

I see only possible explanation, Faggin just was not brave enough, to propose Exxon tops something more brave, like 68k. Or he really was, but they chosen simpler and more traditional design for that time.

Finally, I think, Faggin was tech genius, but looks like, this time some political things overweight to obviously flawed decision.

Does anyone have the history for why number of pins was such an important consideration (not just for Zilog, Intel too)? Was it really that much more expensive to make a 64 pin package than a 40 pin one?

Zilog could get a bigger market share. Still remember those times programming in Z80 machine code. It was much more flexible and convenient versus 8080.

You can find Zilog in embedded systems, they are not dead at all.

> This was even though Intel’s 8086 was, by many measures, a design that was markedly inferior to the Z8000.

I don't see this as true at all. The 8086 segment registers are fine-grained, so you can use the single 16 bit value in a single register as a "pointer" to memory as long as you're OK with your blocks being allocated in 16 byte chunks and don't try to do array indexing on the raw value. This doesn't match the C memory model well, but it's very usable and for years DOS software exploited this trick to get clean addressing across the full 1M memory space of the PC with near-zero overhead[1].

The Z8000 had two-register addresses[2] and you needed to carry those two full words around everywhere. It's equivalent to writing DOS software with the "Huge" memory model pervasively (something pretty much no performance-sensitive software did, historically), because that's all the CPU could support. It's a big, big loss.

And all you get back for your trouble is a bigger register set, which looks great in a ISA document but doesn't really make up for the terrible memory access design. Zilog spent their transistors on the wrong things.

[1] Not zero, because there are only two usable segment registers to hold these pointers, but then the architecture had only 4 true GPRs anyway.

[2] IIRC (and seemingly confirmed by a quick wikipedia check) not even linear ones! The "segment offset" wasn't packed next to the low address bits. So you can't even do natural math on arrays bigger 64kb.

FTA: “One cheaper version would fit into a 40-pin package. This version would have its memory address sizes limited to 16-bits and so would only be able to use 64 KB of memory. A more expensive 48-pin version would have access to a 23-bit or 8 MB address space.

To support this approach, the architecture would be based on segmented addresses.”

I don’t see how that follows, given the example of the 6507. https://en.wikipedia.org/wiki/MOS_Technology_6507

“The 6507 (typically "sixty-five-oh-seven" or "six-five-oh-seven") is an 8-bit microprocessor from MOS Technology, Inc. It is a version of their 40-pin 6502 packaged in a 28-pin DIP, making it cheaper to package and integrate in systems. The reduction in pin count is achieved by reducing the address bus from 16 bits to 13 (limiting the available memory range from 64 KB to 8 KB) and removing a number of other pins used only for certain applications.”

The instruction set of the 6507 can address 64kB of memory, but it lacks connections to the outside world to actually use its full address range (it might even be possible for a hardware hacker to open up a 6507 and add those extra pins, depending on how much the 6507 internals differ from that of the 6502)

The Z80 will always be my first love, in a TRS-80 Model 1 and soon after, the Vector Graphic Vector 3 which was a sturdy S-100 machine running CP/M. Robert Harp of Vector was an extremely competent designer faced with a challenge, a computer with CPU, CRT and keyboard in one unit. All-in-one machines were a challenge because noise from the video stream and HV flyback transformer pervaded the insides, so he restricted the 6 card S-100 cage width to a few inches and found the worst transients on signal lines and placed extra conditioning on the bus, mods reported back to Zilog to assist with future Z80/S-100 builds. The Vector 3 paper manual had 40 dense pages in the back with commented assembly of its entire BIOS. That was a nice touch and I taught myself assembler from it.

> One key implementation decision was that the Z8000 would not make use of microcode. Microcode would have broken down the Z8000’s instructions into a series of simpler instructions, hidden from the outside world, which the processor would execute. Instead, all instructions would be ‘hard-wired’ into the logic of the CPU, a more challenging approach for the designer. Shima would later discuss how much more difficult the Z8000 was to create when compared to the Z80, and how it tested the limits of the tools that he had available:

“… there are so many instructions in Z8000 it is impossible to store all of test vector for debugging in the memory of test bench anymore. Also, MOS process was getting denser and denser and also the size of the defects in masks was getting smaller. That is it was not so easy to find the fully functional die.”

This seems like a remarkable engineering decision to go entirely without microcode. Are there any comparable examples post 1979?

Federico Faggin is a hero

Some friends of mine worked at a startup in the early 80's working on a z8000 based multi-user business system (Proteus for anyone around Vancouver then).

"WITH 418 OP CODES" !

There are a number of things that overlap here: the number of layers on circuit boards was still quite limited if you wanted the board to be affordable (2 layer boards were (back then...) 5x as cheap as 4 layer boards and 4 layers boards were 5x as cheap as 6 layer ones). There is the cost of the package itself and there is the cost of all of the infra around packaging and testing the die, the surface area of the chip die goes up with the square of the sides but the area available for interconnects only goes up with a factor of 4 unless you want to stagger your connecting pad. But that would complicate wire bonding.

Chip packaging has come a very long way from the days when a 40 pin DIP was considered a large chip. Kens (righto.com) has a series of articles about classic chips that show what high density designs looked like in those days and you can clearly see how the limits of packaging play into the designs of the dies themselves.

A 64 pin package that would not occupy a very large amount of board area (this is well before SMD became commonplace) would use all kinds of tricks such as staggered legs (sometimes up to three rows) and really tiny traces to be able to keep the costs down.

This is a fascinating bit of tech history and the fact that the packaging kept pace with Moore's law is maybe not quite as impressive as what was happening on the inside of the package but it was a major achievement and an enabler in and off itself.

From memory the reason given was test machines topped out at 40 pins. Anything bigger was much more expensive to test. IC Testers 40 years ago would apply inputs sequences to devices and check that the outputs were correct. Works for simple logic but already was a problem for processors.

The 8086/8088 multiplexed the address and data busses to get the pin count to 40. Which wasn't bad when using DRAMs since they're also multiplexed. Again to save cost.

Advantage of the 8088 was the 8 bit data bus. So you only needed 8 DRAM chips. Which was a big cost savings. And extra 16k of DRAM could be hundreds of dollars.

Packaging had been a limiting factor for a long time, e.g. the Intel 8008 has the weird multiplexed bus it has, and requires so much external logic, because Intel was largely "just" a memory chip company at the time and couldn't package bigger than 18 pin DIPs.

Prototype carriers were likely significantly more expensive for >40 pin DIPs, just due to the lower demand. The ceramic packages with a die well and glued or brazed lid are available as an off-the-shelf item for low run, prototype, or special chips, and that's what a lot of chips back then started off in, including the Z8000.

As other comments suggest, escape routing was also a secondary issue. Not a problem for "Texas cockroach" 64-pin DIPs, but PGAs and such.

In US, due to cost. Japanese fully embraced SMT in mid eighties, and were already mass manufacturing products with ~100 pin QFP chips https://www.shmj.or.jp/english/packaging/pac80s.html.

I cant find it now, but I remember in one of Asianometry videos a history of Japanese manufacturer traveling to Texas and discovering he can offer American clients his lead frames at 1/10 domestic cost and still make a killing.