They are aiming at 5nm in 2025 and extend it to 2nm in 2027+. I guess in real world terms you can add at least 1 year to it even in the most optimistic scenario.
I dont expect many logic chips will be using it, given the sunk cost involves in all the new and older design with current tools and manufacturing. But if it works it would be very exciting for DRAM and NAND.
Even RPI5s with the Broadcom BCM2712 which is super high volume is 16nm. If they manage to get 5nm in 2026 at low cost than that's the path to take the SOC crown.
This could even lead to RISC-V SOCs/SBCs at RPI power and price tag (yeah, still dreaming).
A little more power (different form factor...) but don't miss Milk-V Oasis.
That's due this summer, $120, mini-itx and should be massively faster than RPi5.
Japan back in control of DRAM, nature is healing
It seems everything old is new again. https://thechipletter.substack.com/p/leaving-arizona:
“there was a reason the 6800 was expensive. It was made using ‘contact lithography’, where the photomask, containing the image that is to created on the silicon die, comes into direct contact with the silicon wafer. This inevitably led, over time, to damage to the photomask, reducing yields and eventually rendering the expensive photomask unusable. Making a low-cost version of the 6800 would be impossible without a more cost-effective manufacturing process.”
Reading https://en.wikipedia.org/wiki/Contact_lithography and https://en.wikipedia.org/wiki/Nanoimprint_lithography, that problem doesn’t seem to have been solved, but of course, it’s possible that the lower cost more than compensates for it.
The 2nd is like embossing, the 1st is like stencil (like other types of photolithography, but the photomask touches the wafer).
https://global.canon/en/technology/nil-2023.html
Would they still have to make a standard photomask and use that to produce a mold using EUV lithography? At which point a cheaper process could be used for production. ASML would still be in that supply chain, but only for mold production.
> In addition to the technology enabling high-accuracy measurement of positional-deviation information, matching technology enabling alignment with lower-layer patterns is also important. Canon has developed a proprietary matching system that achieves alignment by using laser irradiation to thermally deform the wafer (Fig. 2). This system makes it possible to change the heat input pattern and freely deform the wafer by controlling an ultra-fine mirror group called a Digital Micromirror Device (DMD). Instead of assuming that thermal deformation of the wafer worsens alignment precision as is conventionally thought, Canon has applied an innovative new approach to the alignment (Fig. 3).
This is damn cool (hah)! They use a DMD to deposit packets of heat to different parts of the mold to warp to match the underlying layer it needs to imprint for localized nm level positioning. Bad ass.
Am I wrong?
If it takes N days of very expensive process to make a mask and the mask can be used M times with cheaper process, what are the thresholds where it is not cost effective?
https://global.canon/en/news/2023/20231013.html
Canon Says New ‘Stamp’ Machine Will Slash Chipmaking Costs – FT
https://www.asiafinancial.com/canon-says-new-stamp-machine-w...
While everybody is looking at the SOTA factories, manufacturing is still constrained at the bigger nodes, and bringing the cost down at older processes looks like a worthy goal
Also keen to see us build silicon up into the 3rd dimension as far as we can, not stacking chips but just continuing to add more and more layers until z = x = y, similar to 3d printing I suppose, leading edge nodes don't really have the wiggle room for that sort of experimentation.
But a 20mm^2 multi-layer but "flat/traditional" 3nm chip vs a 20mm^3 50nm chunk of silicon layers would be super cool to play with!
So this is the competitive advantage.
High performance per watt, why not all three? Smaller transistors take less power to switch, so they likely can be run at a higher frequency without thermal issues. (Of course, a lot of other design considerations apply.)
In nanoimprint lithograhy, a stamp is pressed into the resist on wafer and leaves the desired pattern behind.
The difference is that the resist is removed mechanically instead of chemically.
For the case of chip lithography they'd probably make source masks, copy the first generation a time or two, and use those secondary source masks to produce consumable 'stamps' for production.
Hopefully the stamps maintain sufficient quality across at least a couple batches (50-100+?) of wafers.
It only touches a liquid photo-resist that is spread on the wafer. The stamp is transparent, which allows UV light to shine though and exposes the photo-resist, which solidifies into a mask matching the stamp.