Each parameter is a connection between artificial neurons. For example, inside an AI model, a linear layer that transforms an input vector with 1024 elements to an output vector with 2048 elements has 1024×2048 = ~2M parameters in a weight matrix. Each parameter specifies by how much each element in the input vector contributes to or subtracts from each element in the output vector. Each output vector element is a weighted sum (AKA a linear combination), of each input vector element.
A human brain has an estimated 100-500 trillion synapses connecting biological neurons. Each synapse is quite a complicated biological structure[a], but if we oversimplify things and assume that every synapse can be modeled as a single parameter in a weight matrix, then the largest AI models in use today have approximately 100T to 500T ÷ 0.5T = 200x to 1000x fewer connections between neurons that the human brain. If the company's claims prove true, this new chip will enable training of AI models that have only 4x to 20x fewer connections that the human brain.
We sure live in interesting times!
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Which, it probably can't... but offsetting those simplifications and 4-20x difference is the massive difference in how quickly those synapses can be activated.
So only 4-20 of these systems are necessary to match the human brain. No?
...
It's meaningless to say something can train a model that has 24 trillion parameters without specifying the dataset size and time it takes to train.
https://web.archive.org/web/20230812020202/https://www.youtu...
(Vimeo/Archive because the original video was taken down from YouTube)
200,000 electrical contacts
850,000 cores
and that's the "old" one. wow.
edit: thanks people, makes sense now!
The peak power average of the 7950X3D is roughly 150W[3], which means if you could somehow run all 450 CPUs (900 dies) at peak, they'd consume around 68kW.
edit: I forgot about the IO die which contains the memory controller, so that will suck some power as well. So if we say 50W for that and 50W for the CPU dies, that's 45kW.
That's assuming you get a "clean wafer" with all dies working, not "just" the 80% yield or so.
[1]: https://www.techpowerup.com/cpu-specs/ryzen-9-7950x3d.c3024
[2]: https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chi...
[3]: https://www.tomshardware.com/reviews/amd-ryzen-9-7950x3d-cpu...
https://www.cerebras.net/blog/whats-new-in-r0.6-of-the-cereb...
"CSL allows for compile time execution of code blocks that take compile-time constant objects as input, a powerful feature it inherits from Zig, on which CSL is based. CSL will be largely familiar to anyone who is comfortable with C/C++, but there are some new capabilities on top of the C-derived basics."
And far fewer blinking lights.
How many early supercomputers / workstations etc would that include? How much progress did humanity make using all those early machines (or any transistorized device!) combined?
4004 from the 1970s used 2300 transistors, so it would have needed to sell billions.
Pentium from 1990s had 3M transistors, so it could hit our target by selling a million units.
I'm betting (without much research) that the Pentium line alone sold millions, and the industry as a whole could hit those numbers about 5 years earlier.
Quote:
Billion is a word for a large number, and it has two distinct definitions:
1,000,000,000, i.e. one thousand million, or 10^9 (ten to the ninth power), as defined on the short scale. This is now the most common sense of the word in all varieties of English; it has long been established in American English and has since become common in Britain and other English-speaking countries as well.
1,000,000,000,000, i.e. one million million, or 10^12 (ten to the twelfth power), as defined on the long scale. This number is the historical sense of the word and remains the established sense of the word in other European languages. Though displaced by the short scale definition relatively early in US English, it remained the most common sense of the word in Britain until the 1950s and still remains in occasional use there.
"4,000,000,000,000 Transistors, One Giant Chip (Cerebras WSE-3)"
So I guess they're trying to stay true to it.
I'm sure those TSVs connect to a huge array of switching power supplies, so the 24kW doesn't travel very far at such low voltages.
Imagine the heat sink on that thing. Would look like a cast-iron Dutch oven :)
In the days before LLMs 44 GB of SRAM sounded like a lot, but these days it's practically nothing. It's possible that novel architectures could be built for Cerebras that leverage the unique capabilities, but the inaccessibility of the hardware is a problem. So few people will ever get to play with one that it's unlikely new architectures will be developed for it.
The Nvidia bandwidth to compute ratio is more necessary because they are moving things around all the time. By keeping all the outputs on the wafer and only streaming the weights, you have a much more favorable requirement for BW to compute. And the number of layers becomes less impactful because they are storing transient outputs.
This is probably one of the primary reasons they didn't need to increase SRAM for WSE-3. WSE-2 was developed based on the old "fit the whole model on the chip" paradigm but models eclipsed 1TB so the new solution is more scalable.
And keep in mind that these nodes are hilariously "fat" compared to a GPU node (or even an 8x GPU node), meaning less congestion and overhead from the topology.
Maybe it wouldn't be as powerful as one of these, due to their less capable fabs, but something that's good enough to get the job done in spite of the embargoes.
Yes.
https://f.hubspotusercontent30.net/hubfs/8968533/Virtual%20B...
- non-sparse fp16 in WSE-2 was 7.5 tflops (about 8 H100s, 10x worse performance per dollar)
Does anyone know the WSE-3 numbers? Datasheet seems lacking loads of details
Also, 2.5 million USD for 1 x WSE-3, why just 44GB tho???
You can order one with 1.2 Petabytes of external memory. Is that enough?
"External memory: 1.5TB, 12TB, or 1.2PB"
https://www.cerebras.net/press-release/cerebras-announces-th...
"214Pb/s Interconnect Bandwidth"
I mean, in a cluster you might have a bunch of nodes with 8x GPUs hanging off each, if this thing replaces a whole node rather than a single GPU, which I assume is the case, it is not really a useful comparison, right?
I trust that gamers will outlast every hype, be it crypto or AI.
* Power Usage
* Rack Size (last one I played with was 17u)
* Cooling requirements
"We call it the engine block because it somewhat resembles a three cylinder motorcycle engine"
(referring to the power distribution and cooling)
Once you've done that, the transistor is on until the gate capacitor is discharged. This requires getting rid of the electrons you stuffed into it. The easiest is to just connect the gate to ground, essentially throwing the electrons away.
So for each time the transistor goes through an on-off cycle, you need to "spend" some electrons, which in turn need to be supplied from the power supply. Thus higher frequency means more current just from more on-off cycles per second.
There's also resistive losses and leakage currents and such.
Now in theory I suppose you could recycle some of these electrons (using a charge pump arrangement[3]), reducing the overall demand. But that would require relatively large capacitors, and on-chip capacitors take a lot of chip area which could have been used for many transistors instead.
[1]: https://en.wikipedia.org/wiki/CMOS
[2]: https://en.wikipedia.org/wiki/MOSFET#Modes_of_operation
Add up trillions of transistors, flicking on and off billions of times a second, and you get enormous power draws.
What is actually drawing power is the gate capacitance of the transistors. If the transistor were a physical switch, the gate capacitance is the "weight" that must be put on the switch to flip it. Of course this weight gets smaller as the switches shrink and as the tech improves, but it will always be non-zero.
None of this accounts for resistive losses either, which is just the cost of doing business for a CPU.
Each gate has logically two transistors of which exactly one is always conducting, either connecting the output to the supply rail making the output a one, or connecting the output to the ground rail making the output a zero. When the output of the gate changes, both transistors have to switch in order to connect the output to the other rail than before. While this happens both transistors are conducting at the same time allowing current to flow from the supply rail to the ground rail.
In addition to that the input capacitances of subsequent gates get charged from the supply rail when the output goes high and discharged into the ground rail when input goes low. So every signal change pumps some charge from the supply rail through the input capacitances to the ground rail.
Crowbar current is still a big problem. Leakage of Finfets are crazy, especially when you use ulvt devices, which you need for high performance.
The previous post is fully correct. Though the bulk of the power is switching capacitor.
- Half of themis power is resistive loses. This is kinda a fundamental thing. Charging a capacitor with a resistor is "lossy".
- Some of the charge is reused within the circuits