Getting more efficient output is a nice bonus.
Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work:
You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version tough, that has some major UI bugs. You want to program a HerpSoft PLC? You need EasyHerpes IDE! What, command line toolchain? Text editor? You must be completely insane!
It's been somewhat of a personal fight against windmills for me back then. That, plus suggesting that we are actually developing software and the C/Assembly/VHDL maybe shouldn't be an undocumented, tested-only-once pile of spaghetti based off a circuit diagram inside one guys head (and no, a 50 line comment block with a German transcription of the code below is not documentation).
You had it good back then. Now it's a one-line comment in Chinese. Line is 300 characters wide. /Yorkshire men skit.
It's that they're the only vendor supported method of working with the parts. If you build your product with an unsupported toolset and something doesn't work, you need to be prepared to reproduce the issue in the vendor support toolchain if you want support.
People coming from desktop and mobile development roll their eyes at this because they aren't coming across bugs in their x86-64 process or M1 Silicon that haven't already been patched over by some combination of microcode, the OS, and the toolchain. Everything works as expected.
Not so in the world of embedded. On modern complex systems, vendor involvement can be a critical part of the development process. Many of the products you have in your house like your router, Wifi gear, and IoT devices were probably co-developed to some degree with the hardware vendor. Starting with the vendor-provided reference design gets you to market much faster, even though you often could forge your own path with a separate toolchain and start from scratch.
It's still this way even in MCU development. You can go out and develop something like an STM32 system completely without STMicro's tools, but it's much easier to start the project in STMicro's tools and copy over the parts you need for setting up everything from clocks to peripherals, then to maintain a skeleton project in the official tools in case your separate toolchain starts acting funny.
PLCs and FPGAs are still pretty damn bad though.
IMHO yes, if not worse.
Working now with some advanced devices from Xilinx (using very expensive top-line SoC. If you change version of the Vivado tools, you have to basically start again from 0 your project. Is a complicated mess because of matching of the OS in the ARM controller and the FPGA part…
Vivado is expensive, bloated, buggy garbage.
The synthesis discussed in the linked page is one of the earliest steps, and from the point of view of open source implementations, the simplest one, because all necessary information is freely available.
Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.
The open source tools still lack too many features to be useful for non-hobby development.
Also looking to their full stack it seem they use VPR/VTR instead of nextpnr for routing. That seems like a backwards choice.
I can't speak for them, so I'm not sure, but I feel like new FPGA suppliers coming around having open source tooling being the default is something that the authors of Yosys would like.
Zero ASIC even credited the original authors in the press release and released the source code, which they didn't need to do. If you release your code under a permissive license, like Yosys did, a company taking it and selling a closed source version of it is something you are allowing. If that's not something you want, choose a different license.
In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.
[1] Consequently, there's more to FPGA synthesis than LUT mapping, so take the reported results with a huge grain of salt.
The closest you'll get is xc7 (Xilinx) vs vendor, one of which is surely Xilinx 7. But the Yosys xc7 support is limited and not the best supported, so it's not a great comparison either.
Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.
We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)
https://github.com/siliconcompiler/logiklib/tree/main/logikl...
https://github.com/zeroasiccorp/wildebeest/tree/main/archite...
For anyone else who was wondering, it says it's under the Apache 2.0 license: https://github.com/zeroasiccorp/wildebeest?tab=Apache-2.0-1-...
I didn't realize that Xilinx xc7 synthesis was officially a feature of Yosys already!
Dropping the logic depth for picorv32 on LUT6s from 17 to 6 seems like it will double the achievable frequency or more. It's especially impressive that this beats the vendor tools—but it's unclear to me if this is an apples-to-apples comparison.
https://github.com/YosysHQ/yosys?tab=readme-ov-file#getting-...
I wish we had a modern easy-to-use solution.
I expect my synthesis tools to consume text and output a netlist and to be able to do that in regression with a Makefile. Is that eighties? Synopsys DC does it, so does Vivado and Quartus and any other synthesis tool, including Yosys.
This can be caused by increased logic usage, if the synthesis tool must create significantly more LUTs to reduce the critical path. This may make it harder to place the logic on the critical path close together, increasing the routing delay.
Additionally, if the synthesis tool replaces something with a dedicated routing path (most FPGAs have dedicated routing for carries, some may have dedicated routing for local connections in a CLB or between CLBs). These dedicated routing connections usually have a lower delay than the general purpose routing network, potentially increasing delay
The figures they have listed look promising though, they're lower or comparable to the commercial tools in terms of resource usage, with lower or comparable logic depths. They do however not have support for things like carry chains, which may potentially make some things like adders slower than the other tools.
And it's because those engineers do not demand. "I Want something easy to use and has GUI, not some Terminal command line"
Please provide a source for this claim. Yosys, for example, can't route [1] designs even for Xilinx 7-series devices, and that architecture has been introduced 15 years ago.
[1] Not to be confused with synthesis, mapping, or placing, all of which come earlier in the flow, and for all of which sufficient information is public available.
It works well enough to build a working litex RISC-V SOC capable of running Linux, for the QMTech Kintex-7 325T board.
I don't think the Cyclone V project has got as far, but I could be wrong. (It kind of slipped off my radar after I realised I was spending way too much time on Discord and purged all but a very few servers to reduce my distractions.)
Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it would have been great. Maybe they even would have acknowledged in the blog post that the stack included binutils :)
They start out by describing all the work that has been done by other people to make open source synthesis possible.
Then they say they've added some well known, industry standard optimizations to the existing open source tools. In addition, they made use of the abc tool in a way that maybe wasn't being done much before.
My view is that if you think someone taking your software, changing some parts, and releasing it under a different name (while still giving you credit in an about section) leaves a bad taste in your mouth, don't release your software with a permissive license. You are explicitly giving permission for someone to do this.
I don't like companies doing this, so I tend to release under GPL. Even then, I'm happy for someone to rebrand and sell it, as long as the source is still shared. I gave them permission to do that.
Don't give someone permission to do something, and then say it's in bad taste when they do that thing.
I don't agree that that kind of permission means you're not allowed to have a bad taste in your mouth. But even if I did agree, that argument only applies to the developer. You are not talking to the developer. We as third parties are fully allowed to complain.
That said, this work is important, you do need it to get your FPGA running. And from the table, the reported optimizations look good (though I haven’t dug into them in detail). Still, describing it as “a synthesis suite” when it’s really “a plugin that adds FPGA support and a few optimizations to Yosys” does indeed leave me with a bad taste in my mouth.
Of course, you don’t have to agree with me. It’s clear from other comments that not everyone does, and that’s totally fine.
When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.
I think they've fixed this only a year ago or so.
On top of that, the "agile" mindset all too often also means there is no coherent vision where the project should go, which can and does lead to bad fundamental architecture decisions that need extensive and expensive workarounds later on.
And yes, there have been people describing exactly that in ASML [1], although the situation seems to have improved [2].