Loongarch Improvements with Box64(box86.org) |
Loongarch Improvements with Box64(box86.org) |
Actual title is "New Box64 v0.4.0 released".
I get you're trying to summarize it, but what's most relevant depends on the person reading.
LoongArch could have instructions that emulate specific x86 behaviour and flags, but there is practically no documentation available.
Basically, will writing against these upcoming chips mean writing one implementation for Qualcomm, one implementation for Rockchip, one implementation for Samsung, etc? Or will it just require one implementation for the standard ARM "switch to total store ordering memory model" extension
RISC-V has an official ratified extension for TSO, and a work-in-progress one for dynamic switching between RISC-V's standard memory model and TSO.