Two Weeks Until Tapeout(essenceia.github.io) |
Two Weeks Until Tapeout(essenceia.github.io) |
Related: I did not understand 95% of what she wrote.
- IC design software (at a startup bought by Cadence)
- an IC (contract out of Dallas semi)
- FPGA HFT acceleration
- fixing some OS drivers for Windows CE
- finding a compiler bug
- various bits of embedded firmware in C and assembly for various platforms
- debugging with a scope
- desktop applications
- a web server (defunct ZWS)
- web apps (Perl. Long time ago)
Somehow I've never written a react app.
Count your blessings.
Never got an offer through "who's hiring" though.
Is it true that we will likely have these 180nm chips for things like light bulbs for the foreseeable future?
Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes.
Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software.
When you combine it with a fixed shuttle date like in the article it is even worse because if you miss that date it might be another 1-2 months for the next shuttle instead of just a day for day slip when you control all the masks.
I don’t work much on apps anymore but I hear it’s somewhat better now.
Another big area is compliance, those processes can take forever.
Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.
I've worked at one huge company where they planned 3 full base layer mask sets and 1-2 metal spins for each full base layer set. This was when doing a chip on a brand new process node where you couldn't always trust the models the fab gave you so you wanted more post silicon characterization to recalibrate models.
In case anyone wants a preview of what to expect.
I love the writing style!
Especially in the project roadmap section..
The licences for proprietary EDA tools are very expensive it seems and most EDA people i talked to didn't really care for any open source tools - as their companies paid for the licenses.
https://tinytapeout.com/chips/tt05/tt_um_rejunity_sn76489
https://librelane.readthedocs.io/en/latest/usage/timing_clos...
Oh, this is fascinating.
The ECOFILLER gate array style cells are easier to use.
Then during the DRC check process in Calibre we run a check to make sure that the base layers stayed the same and only the metal layers changed. Since we have 18 metal layers in a leading edge node hopefully only metal layers 1 to 3 changed for the metal ECO so you only have to pay to make new versions of that.
A full mask set in 3nm can be over $30 million. Just a new set of metal masks is around $20 million.
A full mask run takes about 4 months in the fab. Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers. Then when you do a metal respin they get those out of storage and save a month.
> Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers.
Oh, I had no idea that was a thing.
Blocks are never 100% full. If it was then you would never be able to route the design. High utilization may be 70% but if a block has tons of IO then I've worked on blocks that are only 25% utilized. For various manufacturing and yield purposes the empty spaces need filler cells.
Sometimes we put in decoupling cap cells. But the ecofiller cells go in everywhere else.
About 25 years ago we were using spare gates that we had preplaced on the die.
About 5 years ago we started using spare gates preplaced and ALSO the ecofiller cells. The reason I was told was to save money because the ecofiller cells require some other mask layer to change. I think that was in the $500K range but it's still money.
In general I hate doing ECO's with the preplaced spare gates as it is manual and time consuming to find the best cells to use.
It doesn't benefit from 22nm - analog blocks generally don't scale down at all, they have to be a particular size to achieve particular current handling, inductance etc. requirements. But we need the production line availability.
Does this even work longterm? I'd like to think transparent-by-design hardware manufacturing is not a pipe dream, but if that's the case, I would hate to give it too much thought.
From the 2025 Free Silicon Conference:
https://wiki.f-si.org/index.php?title=The_Transparent_Refere...
https://wiki.f-si.org/images/e/eb/OpenFab%40FSiC2025.pdf
The initiative started in Germany, where the research institute IHP already provides an open source 130nm PDK and associated foundry, but interest is spreading. Here's the abstract from that talk:
"The European Chips Act aims to double Europe’s share in global semiconductor manufacturing to 20% by 2030. However, most current investments focus on leading-edge nodes and pilot lines, which – while important – are not sufficient to achieve broad capacity scaling. At the same time, demand for mature nodes (≥65 nm) remains strong: over two-thirds of chips in automotive and industrial sectors still rely on nodes ≥90 nm, and this trend is expected to persist through 2030. This contribution introduces the concept of a Transparent Reference Fab – a fully open, scalable semiconductor fabrication model designed to serve as a blueprint for sovereign and trustworthy chip manufacturing in Europe. Unlike traditional pilot lines, the Transparent Reference Fab is production-ready and replicable. It includes open access to process design kits (PDKs), equipment configurations, process recipes, and operational know-how. The fab targets mature nodes, especially 65 nm CMOS, and is intended to be built on existing infrastructure to reduce time-to-market and technical risk. We argue that such a model can significantly multiply Europe’s production capacity by enabling private and public actors to replicate the reference fab across regions. This approach would not only strengthen Europe’s position in strategic semiconductor supply chains but also foster innovation, education, and security through transparency. The paper presents the strategic rationale, technical architecture, and implementation path, positioning the Transparent Reference Fab as a critical instrument for European resilience and competitiveness."
We can save money during initial prototyping, by creating a small test structure as small as 1mmm^2, which reduces the cost of a prototype run to 5k$ - 10k$. Some services that provide this are MOSIS [0] in the US, and Europractice [1] in the EU. But when we go to a full production run, there's no way to get around creating a 'full reticle' design, as image sensors have a physical dimension determined by focal plan size requirement of imaging application. For example, in digital camera, if a sensor is 'full frame' then it obviously has to be 36mm x 24mm, regardless of if the process node would have let you shrink it. And if you make a serious mistake, then you need to do another production run, which means you pay the 300k$ - 1m$ once again.
In terms of the circuit functionality, image sensors require a mixture of analog and digital design, but in this area, even many of the digital circuits are custom designed, rather than relying on foundry-provided 'standard cells' and an automatic place-and-route flow.
The other point is of course a next-gen fab first needs to be built, and get those yields up. While previous-gen fab already exists - with all the fine-tuning already done & kinks ironed out. Not to mention maaanny applications simply don't need complex ICs (typical 32bit uC comes to mind, but even 8bit ones are still around).
Regarding node sizes for image sensors, TSMC built a 28nm fab recently for Sony exclusively to make their latest sensors. There was actually a HN post about that a couple years ago [1]. Also, it's important to note that in many applications, the image sensor layer is now actually stacked, with a layer of DRAM (in 45 nm, for example) between, and a ISP (image signal processor) chip on the bottom made in a smaller digital process. You can see an image of that stack up here [2].
[0] https://image-sensors-world.blogspot.com/2020/08/tsmc-report... [1] https://news.ycombinator.com/item?id=24321804 [2] https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-s...
For example, I couldn't find anything about the costs necessary to bring up a fab?