Show HN: We built an 8-bit CPU as 2nd year EE students

Show HN: We built an 8-bit CPU as 2nd year EE students(github.com)

34 points by CorRupT9 2 days ago | 7 comments

Hi! me and my friends together built an 8 bit CPU implemented in Logisim purely from scratch. The control unit of this system does not implement the generic microcode ROM or any kind of RAM. This was made purely from discrete logic gates and coded the system to run different programs.

key features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers

Hardwired control unit built entirely from AND/OR gate logic matrix

Dual-phase clocking to eliminate race conditions

Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional branching that saves upto 25% cycles when conditions aren't met

Full design specification document with version control

Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers. There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.

There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.

To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.

We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.

Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.

Please take a look at it at https://github.com/c0rRupT9/STEPLA-1

For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion https://tcfdiq.gumroad.com/l/zyyux Thankyou!

osigurdson 23 minutes ago |

A 2nd year project back in the day was to build a 4 bit CPU on a breadboard. We had the advantage of having an ALU IC but was still quite tough to get working!

gabrielsroka 2 hours ago |

Ben Eater's SAP came from "Digital Computer Electronics" by Albert Paul Malvino and Jerald A. Brown

https://en.wikipedia.org/wiki/Simple-As-Possible_computer

peterus 1 hour ago |

Awesome project, re fpga implementation one option you might want to explore are used Bitcoin miner control boards if you want the best logic units/$ ratio. I've used the EBAZ4205 (zynq 7010) control boards with a cheap/generic FT2232HL dev board and it works great. Of course it's a bit more of a pain compared to a regular dev board

wildzzz 1 hour ago | |

If they are taking digital design classes, they'll probably be given something like a DE0-Nano that can run this just fine.

HerbManic 2 hours ago |

With all the talk about developers being lazy and younger folk not understanding the technology they use, it is always great to see examples of core foundational work still being done. Makes the rest of that talk feel like fear mongering.

dreamcompiler 31 minutes ago |

"This makes the machine transparent in a way that microcode-based designs cannot be."

Every output bit m of microcode can be equivalently expressed as a logic function of n inputs where the microcode has n incoming address lines. This no less transparent than pure logic if you know the contents of the microcode. Microcode is often preferred because changing it is much easier than changing a bunch of gate logic. IMHO factoring your design into registers vs. control signals and putting the control signals into microcode makes the design more transparent than having a giant sea of gates.

momoraul 2 hours ago |

the rom-to-ram bootstrap is a nice touch. after it hands over, what stops the bootloader from writing to I-SRAM again? a mode flag in the control matrix?