Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm(semiconductor.samsung.com) |
Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm(semiconductor.samsung.com) |
The fact that this level of precision can be achieved on 300mm wafers over many dozens of separate steps in separate devices is an insane achievement on its own.
Yet everybody seems to think the moat is with the AI companies or nvidia.
Generally speaking both HN and the internet rarely appreciate hardware advancement.
I don't think a optics engineere can train a frontier model.
But also a frontier model requires a lot of compute.
The big issue today is leakage currents. They typical account for around 30%-50% of total chip thermal budget, and they get increasingly difficult to control with smaller devices and lower voltages. They're also get worse with increased temperature(!).
The stacked devices here aren't the worst for leakage currents, but they're not fantastic either. Look at the 2nd graph in section 5: You'll see that the current never drops to zero over the range of gate-source voltages (for V_DS=0.7V). The minimum point is the best-case leakage current, and you can see it's well above zero! (The units on the vertical axis of the graph are unknown btw: The label reads as "current drain-source, arbitrary units")
Reducing trace length seems to be the way forward for faster/larger circuits. Signal propagation time on-die is becoming an issue.
Things like Huawei's Logic folding, or TSVs, and so on, attack the issue by reducing signal travel time.
This looks like another building block in that direction.
There's also some push at cooling chips from both sides.
https://semiengineering.com/the-race-to-replace-silicon/
https://www.plantengineering.com/semiconductor-material-that...
The big barrier remains heat and this 3D stacking (aka CFET) makes heat worse by increasing density. It's possible much of the density gains offered by CFETs will remain unutilized unless other approaches to solve the fundamental heat problem are found, possibly discovering new high-conductivity MDI materials.
Really? someone tell that to my city
Retrofits are insanely expensive and often fraught with issues.
Stacking means keeping the same size, but adding more of it so it matches the same compute power as the more advanced smaller chip designs.
China (who is banned from buying from ASML) is currently pursuing stacking as a short to medium term strategy until they can catch up to TSMC.
They’ll keep pushing till you push back.
As an aside, my old Westinghouse fridge shows me ads. The ads arrive in my mailbox and then I put them on the fridge with a magnet. One of the ads on my fridge at the moment is for Dominos.
And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.
Not if you replace that length with more capacitors stacked on top of each other.
I've been naively assuming they are now making high quality vias, so that circuit characteristics would be similar in either vertical or horizontal direction.
You must be thinking of something else
In semiconductors there is a positive feedback between temperature and the current that passes through them, so once a certain threshold is passed, the current and the temperature grow very quickly until the semiconductor is melted. This is opposite to the behavior of metals, where resistance grows with temperature, tending to limit the current that passes through the metal, when it overheats.
The currents through the transistors of SOTA logic gates are very small, but their volumes are also very small, so the power density is similar to that in high power transistors.
Thus thermal breakdown that leads to silicon melting is easily achievable. This is why any modern CPU has on-die temperature sensors, so that temperature is monitored and power dissipation is limited, to ensure that the threshold that triggers positive thermal feedback is never reached.
what type of people look at heat transfer at the device level in an IC (and at such short time scales)? where can i learn more about that? this looks like it could have an impact in analog power circuits, because even if you don't destroy the transistor you could alter its characteristics, but i haven't seen a lot of attention being paid to that. personally i guess i figured individual transistors never went significantly beyond the temperature ranges we already consider for the circuit as a whole.
thank you for sharing
Above a certain temperature threshold, the electrical resistance of semiconductors drops exponentially with temperature, which is why NTC (negative thermal coefficient) thermistors are made of semiconductor materials.
This causes a positive feedback loop that increases the current very quickly and concentrates it through a narrow channel through the semiconductor (so the current density can be extremely high even when the total current is still low), which can easily reach 1500 Celsius degrees, melting the silicon, while the temperature of the package and of the solder remains very low (because the time is too short for the temperature to propagate outwards from the melted silicon channel).
For metals the electrical resistance increases with temperature, causing a negative feedback that limits the increase of the temperature, while for semiconductors the electrical resistance decreases with temperature above a certain threshold, so once that threshold is reached positive feedback increases the temperature very quickly until the semiconductor is melted, unless there is some protection system that limits the power dissipation through the semiconductor.
That is why it is very easy to melt silicon in an integrated circuit or in a discrete device, despite its high melting point.