IBM debuts sub-1 nanometer chip technology(newsroom.ibm.com) |
IBM debuts sub-1 nanometer chip technology(newsroom.ibm.com) |
Continuing the well established trend of making bold claims about physical dimensions that have nothing to do with any of the structures in the chip, and the name scales better than the tech.
What they actually deliver is a "nanostack architecture" built with ~5nm features that according to them is comparable to a hypothetical real sub-1nm chip.
It's an impressive achievement nonetheless but it looks like the industry has a few too many marketers.
It describes density measure where you can compare it to planar transistors from the 28-nanometer (28 nm) node around 2010 to 2011. A "0.7 nm" node has equivalent density as if we could have shrunk standard flat transistor node down to 0.7 nanometers.
For silicon, the gate length of a FET has a lower limit somewhere between 10 nm and 15 nm.
The current CMOS manufacturing processes have not reached the limit yet. For making smaller transistors, a transition to other semiconductor materials will be necessary.
The vertical thicknesses of various layers may be of only a few nanometers or even of a fraction of a nanometer, but that does not matter directly for the circuit density.
The supposed node size refers to horizontal dimensions, not to vertical dimensions.
Vertical dimensions of around 1 nanometer or less could be achieved already many decades ago, because they depend on growth speed and on time, not on lithography, like the horizontal dimensions.
The industry should have stopped decades ago to talk about the "size" but they should have characterized a CMOS process by its density, e.g. in logic gates per square mm.
However, an actual concrete number would be disliked by marketing, because they could no longer claim that their "1 nm" process is better than the "2 nm" process of another vendor, if their density is not really better.
I know they won't go for an anything that makes as much sense as 5nm3, so I vote for "1nm hyper space"
Different companies measure it differently too. This was a while ago, but I remember reading that Intel 10nm was more or less close to TSMC 7nm. I'm sure this is still true to varying degrees.
We care about PPA (power, performance, area) and not how large or not-large features actually are. Comparing gate lengths between a 1980s planar transistor and a 2010s 3D FinFET or GAA transistor is obviously nonsense, the relatively aligned node names of the industry actually do make sense as a shortcut here.
Broadly speaking yes, this is the business model. IBM has been at this for many years with technology transfers, licensing agreements, support and other arrangements. Rapidus, Samsung, GlobalFoundries, ST, SMIC, AMD, etc. have all used IBM R&D work at various times for various nodes and products.
The cutting edge of semiconductors is a writhing mass of copulating tapeworms, and IBM lives deep inside that ball. For IBM, what this means is that when you buy one of the ASML machines to make products with this process, you'll pay IBM for the knowledge and support to actually get it working, or give them a cut, or something else, TBD, as circumstances warrant.
Is there a limit to how small things can go? A single atom?
Is there a physical/molecular limit to Moore's Law?
I'm guessing that this is the technology that is developed by Cymer (ASML subsidiary) in California, correct? Is there competing technology? I know xLight is trying to make some inroads on their own version of this EUV tech. I have not heard about any progress though.
also, I was expecting to see cfets mentioned.
So many breakthroughs in hard drives, chips, transistor density, and other aspects of computing have come out of their labs.
Great to see them continuing to innovate.
But, yeah, usually they partner and license. Over the years, they've spun off more and more of their hardware businesses.
I wonder why isn't this more common.
Why? What's their real size?
Not doubting you, just trying to understand and also trying to assess how exaggerated the marketing is.
Currently thrown around numbers mean the "equivalent performance/density" or something like that.
Otherwise, that chip tech sounds really awesome - at least for the future!
1 Å = 100 pm. 1 pm = 0.01 Å.
1 angstrom = 0.1 nanometers, 100 picometers
1 nanometer = 10 angstroms, 1000 picometers
Once you make the gate of a transistor small/thin enough, quantum effects take over. Electrons will randomly teleport into and through the gate causing the transistor to conduct when it shouldn't. I don't have numbers to hand, but it's on the order of a few atoms wide. There's really nothing that can be done about it either, as far as we know. Electrons just aren't physical objects at this scale, you can't simply exclude them from any given volume of space. The electron wave function will simply just appear wherever it wants (within the electron probability cloud). The only way to stop it is to make your insulating junction thicker than the probability cloud.
I don't know which is more ridiculous, the fact that reality works like this, or, that a species of apes was able to figure this out.
Yes, single-atom manipulation has already been demonstrated:
* https://en.wikipedia.org/wiki/IBM_(atoms)
Can you make transistors using that technique? Can you smaller?
Beyond that, engineering a quark-gluon plasma as a processor? I'd watch that Star Trek episode. (we might fantasize about stuff like that but we're roughly monkeys smashing rocks together in a cave vs. building an iPhone sort of gap away from that kind of thing unless somebody has a really good idea)
You also have quantum computing, which I think can/does use subatomic particles? Not sure about that one
However, version 5 of the standard already deprecates that code point and has it normalized into the code for the Swedish letter U+00C5 Å `latin capital letter a with ring above`
Another type of quantum computer uses qubits consisting of "quantum circuits" which are actually huge macroscopic constructions (> 1mm).
Wait, what? How does this work in principle for storage? You can store electrons but you're saying you can store photons too?
The intended meaning of "0.7 nm" is that if you compare the transistor density per area of a "0.7 nm" manufacturing process with that of a "350 nm" process (like used for some Pentium II CPUs, at a time when "350 nm" was a real length), the ratio between the transistor densities is (350 nm / 0.7 nm)^2 = 500^2 = 250,000.
However, for many of the modern node names even this computation is not really true, because marketing may have chosen an arbitrary name that is smaller than for the last process of the main competitor.
Per IBM: "IBM Research at Albany [...] includes more than 100,000 square feet of semiconductor fabrication space"
I guess that is technically a R&D fab not a production one, but they definitely have in house fabrication capability
My understanding is that ASML's acquisition of Cymer in California (the actual EUV light source technology) in 2014 was only permitted under a strict technology sharing and export agreement with the US government. And that the technology development and production had to remain within the US.
The USA CHIPS Act and NY State have provided $100 billion+ in funding with the expectation that ASML's core R&D and "prototyping" like this will be done in the US in partnership with US companies (like IBM).
(In the same way that meter jumps three orders of magnitude to kilometer[1], or millions to billions to trillions, etc.)
[1] Technically there are intermediate SI units between meter and km but nobody uses them. There are not intermediate SI units between the tiny ones.
We have centimeter (10 mm) then decimeter (100mm) then meter (1000mm). Then we jump to thousand again (kilometer).
Does anyone actually use those? I think I would throw up a little in my mouth if I saw either of those on a mechanical drawing.