Is x86 ready to ACE it?

Is x86 ready to ACE it?(chipsandcheese.com)

34 points by mfiguiere 3 hours ago | 4 comments

aidenn0 26 minutes ago |

With 8kb of registers for just this one feature, what does a modern process-control-block look like?

monocasa 17 minutes ago | |

On x86, basically whatever XSAVE writes out.

FWIW, I wouldn't be surprised if you only have a couple threads using this at a time max since it looks an awful lot Apple's AMX/SME stuff. Those Apple execution units only have single engines shared about per cluster.

XSAVE lets you not bother saving register state that user space hasn't changed at the granularity of each large feature.

supriyo-biswas 48 minutes ago |

Great article. What does the (organizational) process look like to convert one of these specs to a processor product, does it go through a committee like the C++ standards?

deadmutex 26 minutes ago | |

> AMD, in partnership with Intel and the x86 EAG (Ecosystem Advisory Group) [EAG24], is readying ACE as the standard matrix acceleration architecture for x86, further enhancing the already vibrant x86 ecosystem.

Source: https://x86ecosystem.org/wp-content/uploads/2026/03/ACE-Whit...