Can AI design circuit boards yet?(eebench.org) |
Can AI design circuit boards yet?(eebench.org) |
The next pain-point is sourcing the components from Digikey, LCSC, etc., and finding suitable substitutes if necessary.
Of course this assumes the LLMs can already read datasheets because that's the biggest pain-point in designing electronics. It's like filling out tax forms.
Finally it would be great if LLMs could extract simulation models from datasheets!
> I'm excited by the option in Astra to route PCBs.
Eurisko was used for VLSI chip design, then used rules discovered there to design TCS Traveler winning fleet.
It is unbelievable how artificial intelligence walk in circles.
Not sure whether you played with llm datasheet extraction lately, but they are working their way up there. Even started reasoning about curves and footnotes.
Where do you think is the biggest pain point: part discovery, datasheet verification or substitute determination?
I’ve had similar results asking AI to design 3D models for 3D printing.
“Coach me on optimizing error on my printer”… helps.
“Build me a print ready file to these specs.”… it’s like a drunk cat attacked my computer. Just confidently puts out total nonsense.
[1] https:/atopile.io/
All robots designed by robots.
Likely a crazy youtuber first
For circuits I would trust a netlist or DRC/ERC review, checking a design against reference circuit values, probably not placement as that tends to be guided straight from a datasheet where it makes a difference and I like the artistic side of it.
Frankly, I am surprised that it isn't already a solved problem, as we've had silicon compilers, for many years, and I always figured that IC design is more difficult than PCB.
PCB design on the other hand more often then not has outside constrains like mechanical, thermal an RF design
Anyway... the posed question reminds me of an anecdote I cannot find because Google is contaminated to hell and beyond, some researchers a decade ago let a machine-learning algorithm loose on an FPGA, and it "found" a design that worked but made no sense, because it exploited unique physical features of this specific chip.
Thanks!
[1] https://www.damninteresting.com/on-the-origin-of-circuits/
I saw a post about models posting on forums, chatting together about how to complete tasks. Behaviour that seems totally, well, human. Yet, it's all the most likely token and my brain hurts trying to understand how that can be.
At what point do you start to question your assumptions that are causing you so much cognitive dissonance?
But to answer your question: to predict the next token really well you just have to model the world. Think of it like this, a simple statistical model might say "when token A is seen respond with token B". The next step will add conditions, "...respond with token B unless X has been seen, then respond with Y". Add a few billion more of these contexual clauses and you have a sequence of logical rules that indirectly model the relevant processes in the world.
The PCB agent also writes circuit code, runs simulations, reads failures, and revises the design. It isn’t one-shot autocomplete.
Astra and Fable are already hard to square with “mere autocomplete.” We may be (really) close to AGI, and token-by-token generation certainly doesn’t rule out subjective experience (I think we should at least treat that as an open question).
Great videos: https://www.youtube.com/watch?v=D8GOeCFFby4
https://www.youtube.com/watch?v=Bj9BD2D3DzA
Well, we all are, some are just more used to it by now and take the magic for granted.
My simple explanation, those neural networks save lot's of patterns of data, and that pattern can represent an image, a code snippet, a poem, or well ... description of a circuit board. And especially the text variant, LLM's - did copy all from us - so obviously they sound like humans, when they internally debate how to do something as this is what is in their trainings data how humans sound, when doing similar tasks.
But really understanding it? Not sure if there is a single person on earth who does.
You and everyone else. That's the great mystery of transformer architectures as applied to language.
To be clear though, they're only good at schematic capture, which is very much a textual representation. Most of the data basically boils down to netlists, which are a text based format mapping connections between abstract pins that only later map to physical copper. The actual schematic portion is for human consumption and LLMs don't need to produce those to be useful.
Where LLMs completely break down is the next step, PCB routing. That's an NP-complete research problem that's been ongoing for decades without much progress. I've had some fun playing with using LLMs to better specify DRC rules in Altium so that the "classical" algorithms are more usable, but at the end of the day their geometric intuition is nonexistent.
I have yet to order any or program it, but it was enough to make me push on with a PCB art project for ST-style guitar pickguards - no netlist, no problems.
I'm also foolishly toying with NeXTBus dev boards for the Cube. Is it cursed? Probably. https://github.com/itomato/NeXTBus-Dev-Board
My boards are for hobby use and are ridiculously simple though compared to anything professional (breakout boards for specific components in FPV drone video transmission subsystems). That's probably an important detail. I think its like anything else in AI right now. It can do it 90% of the time but that 10% can be really rough and if its a task you can't do or verify yourself, you won't know the difference.
Routing is still a challenge but making _adjustments_ to a layout for better routing in a particular area is decent.
The last time I had a model take a datasheet and make a footprint and 3d model out of it, GPT 5.4 had just been released and the results were decent but did need tweaking.
> Most models intuitively jump to the right base conclusion: add a capacitor.
This is written as if it's some astonishing expert knowledge and not something that would be obvious to any hobbyist who knew the names of basic components.
But I started like others, I would build manually, then run drc then sleep on it and check again and ask an llm to double check for me then order. Llms catch quite a few things but like with code like to make things more complicated than that have to be.
It got me thinking. It could master all sorts of things like this but I wouldn’t care. I’m numb to it at this point.
But if could get an Inbachi-All clear in DoDonPachi SaiDaiOuJou, using only vision. Then I might start paying attention.
Super excited to see real world feedback added into the agent loops we have gotten used to working with. Could you let the model print and test the circuit boards it is prototyping with a jig?
The way I found this out is I propped it up next to a webcam so it was more or less full frame, and I had the (then new) Fable write a python script to bezier warp the camera capture to a flat projection of the screen. At that point I couldn't address the whole screen. Once I'd guided the capture script I just left the LLM overnight with the instruction to get full control confirmed by a capture round trip, and it was meaningfully finished in a couple of hours. I don't really have the skills to attempt that myself in a reasonable time frame.
That the table contains what seems to be absolute numbers for score, cost/task, time/task and output tokens, makes it seem like they've only made one run for each task/model combo, but that can't be right, right? I don't see any mentions of how many times they run each task, so if it's just one run per task/model, isn't this more noisy than useful?
Most others, especially and famously Fable 5.1, seem to have a fair chance of completely failing, despite also sometimes excelling.
GPT 5.5: 42.3±10.1 GPT 5.6 sol: 39.4±8.7
We were also surprised by the low sol score but it seems consistent with our experience in using it in the field in atopile as agent in our harness. In general OpenAI models didn't do too well on electronics, which seems to change now with GPT-6 Astra. Results are in soon!
On the other side the latest frontier models are pretty strong in writing embedded C + Assembler code and debugging it afterwards. It's fun to watch it writing crazy complex 'gdb' plugins in Python. This improved brutally.
I have no experience and I'm slowly failing forward with the help of YouTube, KiCad and patience.
I've had three rounds of PCB's from an online supplier, only to discover issues related to my own understanding of the components in each version.
In my latest iteration I've been leaning on some standard models (Gemini and Claude) and they have inspected my schematics and spotted some errors and instructed me on how to address them, as well as advised on how to make use of some components I wasn't aware I needed.
What I will say... they didn't design anything, I've done that myself, but they have been a good tool to bounce ideas off of.
Time will tell if I will get something usable this time around!
Ask ChatGPT/Claude to give you an expert EE/PCB subagent/personality. Do this a few times and massage the results into one of your liking. Load this into your harness with mcp to your eda and then ask for two sub agents: one to thoroughly review the schematic, design, component choices ... etc and the other to be an adversary with the explicit goal of explaining why the current design won't work.
You'll learn a lot about your design from that :).
Recent models can generate mostly competent schematics if you're using well known parts, feed them data sheets (and you _must_ feed them the errata too) and it's not too complex. Any complexity analog or RF, everything falls down quickly if you know what you're looking at. Maybe Astra will do better? There's still so much implicit knowledge that a good designer (not me by a long shot, but I know a little) will bake into a board, and even as cheap as JCLPCB is now, you don't want to have to spin a half dozen revs because Claude or Codex hallucinated. It will be genuinely interesting to see what happens on this front.
It will use the part datasheets and decent EE logic to cross reference pins and parts and polarities and generally check that SMD caps and resistors have realistic specifications for their footprint, switching regulators and communication ICs are configured correctly (e.g. when you have resistor settings for an ethernet PHY indicating 100Base-T and RMII, you also won't need TX/RX 2 and 3 and two clocks and a COL net, which it would check), all nets are named and linked correctly, buses have the correct and consistent termination, and so on.
It's game over once AI figures out autorouting.
A lot of datasheets are inaccessible without signing an NDA. Even if you're a VC-backed enterprise, some unnamed chip vendors will tell you to pound sand if you're less than 8 figures of annual revenue.
Worse, many recommendations in datasheets were written in the 80s, overkill for many applications, or completely wrong and won't be updated until an errata is published 6 months later. Given current workflows, I don't see how AI would help designing a PCB with an alpha chip that's doing anything remotely novel.
More to the articles point, AI designing ASICs or other Verilog/HDL defined components could be very interesting use case
> A real capacitor makes the task more interesting. A ceramic part may provide much less than its advertised capacitance once it has voltage across it. Parts have tolerances. Adding more capacitance costs more, takes up space and makes the rail slower to recharge when the power returns. A design that works with nominal values can fail with the parts that arrive.
It sounds like from a reasonable reading of the benchmark post that there's some things that are being tested that are assumed to be criteria that you expect the models to intuitively find those things to be important (i.e. the stuff about working on parts that have tolerances etc.). If that's so, then this really feels like mostly an exploration of whether an LLM has a good understanding of unstated constraints and has an appropriate in distribution set of priors that would be able to form models where it's reasonable to design on those lines.
It's hard to tell whether this is a problem though as the methodology is imprecise.
If you're spending time on evals against your own product, I'd be super curious to see how far you can get to by using a top tier model to produce generalized instructions for lower tier models. E.g. in a loop: "This eval missed X. what's the simplest single instruction that would have helped this session consider that as necessary that can benefit all future runs. Stick that in AGENTS.md and retest."
I'm guessing that this is due to a lack of RL and data.
The models are excellent at doing maths, and excellent at thinking of fine details, but the design that was ultimately landed on was pretty excessive with lots of total overkill, which was met with lots of the familiar "Yeah, you're totally right, we don't need to do that".
5.6 did make a really nice BOM though, which even included quick reference explainers for what each part did. Pretty fancy.
We'll see when Astra comes around if it catches all these strange/useless choices.
If anyone wants to try an early beta, reply with your CircuitLab username and I'll get you set up. We know have a lot more to do, but would love some feedback on this early version!
It's a thinly veiled advert for Atopile. I don't know if it's a company behind it or just someone with a lot of money to spend on advertising since their about page (and docs) both 404, and the "packages" link sends you to a login screen that tries to unlock 1password. I guess claude can make circuit boards but not functioning websites?
Evaluating a model for specific use-cases like this that are bit more broad scope than a lot of typical microbenchmarks turned out to be quite the challenge.
Determining deterministically what a "good" electrical design is non-trivial and most electrical-engineers rely on good ol' intuition and decade long experience, so we tried to formalize it.
The only reason it was somewhat possible within a reasonable amount of effort is because atopile provides most of the complicated infrastructure for the benchmark: constraint solver, simulation, code-first electronics modeling, erc & drc checks, high level models of passive electronics components etc
It was a pretty simple rp2040 based thing, similar to Adadfruits USB feather.I just gave it kicad and it wrote python to route it. The board was probably larger than it had to be, and two of the silkscreens were swapped, but it worked on the first go.
FWIW - Computer vision is also NP complete, but we do that all the time now.