This article from Aug 2026 says 20 layers are for complex designs. https://www.pcbasic.com/blog/pcb-layers.html. So 124 layers looks like a huge increase.
Not my area, probably got it all wrong, hope this is useful.
OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM
Since the latest semiconductors process an enormous number of signals and the number of wafer-mounted chips increases due to process miniaturization, it is necessary to increase density and more layers on the PCBs used in inspection equipment.
In their linked semiconductor testing page[1], they mention conductive paste. So seems they test whole wafers by having the whole wafer put on such a PCB, using conductive paste instead of solder or similar, and the high layer count is then to be able to bring out all the connections (pins) from each chip to the testing circuits while maintaining the high signal integrity required for the high-speed signals.
That's my semi-informed take.
Higher density chip packing is only one advantage. Unlikely going to see such things in cost-optimized consumer products. =3
The number of layers isn't even remotely close to being a constraint. The real i386DX was manufactured on a process which only supported two metal layers, and a PCB version isn't subject to the same constraints as silicon.