Between ASICs and FPGAs there exists... (wait for it!)... CGRAs!

>"Through the 2000s, the designs grew larger and more tightly integrated. ADRES coupled a VLIW processor with a reconfigurable matrix; TRIPS explored a polymorphous array capable of exploiting instruction-, thread-, and data-level parallelism; and PACT XPP offered a self-reconfiguring commercial fabric.[7][8][9] From the 2010s onward, research emphasized data movement and system integration: HyCUBE introduced a single-cycle multi-hop interconnect, Plasticine organized computation around pattern compute and pattern memory units, and the stream-dataflow (Softbrain) model decoupled memory streaming from the spatial datapath.[10][11][12] The same period saw an open-source ecosystem take shape, including ultra-low-power edge arrays such as OpenEdgeCGRA, which is integrated with the X-HEEP RISC-V microcontroller in the HEEPsilon platform to give a complete flow from C code to hardware.[13][14]

A handful of CGRAs have reached commercial silicon. Samsung’s Reconfigurable Processor (SRP), derived from ADRES, has appeared in systems-on-chip and in ultra-low-power biomedical variants;[15][16] SambaNova commercialized its reconfigurable dataflow unit (RDU), a large dataflow accelerator built from pattern compute and pattern memory units and aimed at machine-learning training and inference.[17]"

Never knew about their existence... until reading this article...