Update on STM

Update on STM(morepypy.blogspot.com)

138 points by wisesage5001 12 years ago | 5 comments

nn4 12 years ago |

Obligatory anti STM hype links:

http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...

Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.

kazagistar 12 years ago |

Is there any plans to work hardware transactional memory into the mix?

kingkilr 12 years ago | |

Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.

4buser 12 years ago | | |

Even new Intel Haswell's STM?