The widening gap between memory and core speeds suggests to me that traditional RISC philosophy is not the way forward for performance and efficiency; fixed-length instructions, load-store restrictions, and delay slots may make implementation easier and faster at a time when memory could keep up with the CPU and instruction decoding was the bottleneck, but now that memory is often the bottleneck, it makes sense to have more complex, dense instruction encoding and the other features that are usually left out of RISCs, but improve code density.

Variable-length instructions are especially beneficial to code density, since often-used instructions can be encoded in fewer bytes, leaving rarer ones to longer sequences. It also allows for easy extension. Relaxing the restriction on only load/store instructions being able to access memory can reduce code size by eliminating many instructions whose sole purpose is to move data between memory and registers; this also leads to requiring fewer explicitly named registers (since instructions reading memory will implicitly name an internal temporary register(s) the CPU can use), reducing the number of bits needed to specify registers.

Other considerations like number of operands and how many of them can be memory references also contribute to code density - 0- and 1-operand ISAs require far more instructions for data movement, while 3-operand ISAs may waste encoding space if much of the time, one source operand does not need to be preserved. 2 operands is a natural compromise, and this is what e.g. ARM Thumb does.

This is why I find the description of "compressed RISC-V" linked in the article ( http://www.eecs.berkeley.edu/~waterman/papers/ms-thesis.pdf ) interesting - benchmark analysis shows that 8 registers are used 60% of the time, and 2-operand instructions are encountered 36/31% statically/dynamically. These characteristics are not so far from those of an ISA that has remained one of the most performant for over 2 decades: x86. It's a denser ISA than regular RISCs, and requires more complex decoding, but not as complex as e.g. VAX. I think the decision to have 8 architectural registers and a 2-operand/1-memory format put x86 in an interesting middle-ground where it wasn't too CISC to implement efficiently, but also wasn't RISC enough to suffer its drawbacks. I'd certainly like to see how an open-source x86 implementation could perform in comparison.

I can understand RISC-V's use in academic settings or if you truly want open hardware.

But what's the commercial benefit? Its an open core, its lacking patents because the performance critical aspects have been patented by others in their designs, so how does this stack up in terms of performance? Can you make a processor design as fast as proprietary ones like the Linux effort?

Second comes the issue of fabrication, is there somebody ready to fab this? Or are you just going to throw this on a large FPGA? If you're throwing it on a FPGA, then why take jabs at the other ISA's when you'll be running this on non-open proprietary sillicon anyways.

Lastly, who cares? I'm guessing embedded is out as they care out the cost of each chip, the cheaper and more performant the better. Perhaps you're running something mission critical or are totally tied to a architecture, but then you're a dinosaur, the industry's trending towards abstracting the hardware away anyways. Do you really care which piece of sillicon your app runs on?

All of the above's probably really biased, misguided and wrong, but I'd like to hear what other HN'ers have to say.

Related recent discussion about an in-progress implementation: https://news.ycombinator.com/item?id=8137521

Looks cool! Disappointed that there's no option to trap on integer overflow. Languages don't support it because processors don't support it, and processors don't support it because languages don't require it; a vicious cycle that someone needs to break.

The dirty secret is: nobody cares because the ISA doesn't matter.

When programming a modern microcontroller, I regularly think: "Gee, I wish I had more pins." "Gee, I wish I had documentation on that peripheral." "Gee, I wish I had better tool support." or "Gee, I wish I had more RAM/Flash/MHz."

I never think "Gee, I wish I had a better ISA".

I applaud the effort to make an open microprocessor especially in light of the increasing efforts to put trusted module crap in our computers. However, this has no commercial advantage in any way other than that.

RISC-V is looking very hopeful, I hope I can get in on some chips soon.

If there were a fully open hardware/software machine, I would give it all of my money.*

*Of budget allocated for purchasing computing devices.

> The dirty secret is: nobody cares because the ISA doesn't matter.

I disagree!! While normal operations don't matter, think about features like 'trap on integer overflow', if it was widespread in the popular ISAs we would have language which would use this semantic and as a result less bugs.

Another interesting feature could be Azul's Vega realtime GC support but I don't know if this requires a change of the ISA, or if it's just a MMU feature..

Hardware capabilities/segmentation would also require support in the ISA.

That said I agree with you that the RISC-V is just 'yet another ISA' which doesn't have interesting technical features, it's main feature is that it is open and you can implement it without paying someone for the privilege.

In this case, an open ISA would allow more stability over time. More over, once we have an open and widely adopted ISA, one can build an open microcontroller. After that, embedded developers will stop getting bad surprises when some specific microcontroller is being deprecated / out of stock and the whole board (and likely large parts of the firmware) has to be redesigned.

And you're right: an ISA don't matter. It could be ARM, AVR or OpenRISC / RISC-V, but it's very desirable to be stable and embeddable into a SoC without purchasing additional licenses.

> I never think "Gee, I wish I had a better ISA".

After programming with AltiVec, going back to MMX/SSE made me wish I had a better ISA.