11 years ago |
11 years ago |
One problem is that there are several layers of abstraction between the electrons and the working of a computer, and the activity of the electrons is rather irrelevant to the activity of the computer, both in actual terms, and for understanding.
An interactive simulation could show what happens at the various layers, and perhaps what you'd want is to see all the layers in parallel, but here we have a difficulty for this representation, because those layers actually work at very different time scales, which cannot be visualized (with an interactive simulation) easily, unless you have a million years in front of you.
http://paste.lisp.org/display/139933
About binary numbers, what we can say is that in certain circumstances, it is more efficient and safer from a physical engineering point of view, to use only two different states to represent information elements. Which leads naturally to mapping the abstract, mathematical notion of binary digits, {0, 1} to those pairs of physical states. Notice that I don't say tensions, because sometimes it's current, and sometimes it's charge (eg. in condonser-based memories, like DRAMs).
But notice that when transmitting data eg. with modems, or even with more modern options such as ASDL or optic fibers, engineers actually use more states, more than two different symbols, to attain higher bit transmission rates. cf. https://en.wikipedia.org/wiki/Baud
Therefore you should realize that at the electronic level, engineers do not always use two states, so the notion of bit is not too relevant to computing: it's only something that matters at some low-level layers. Computers usually work at layers where it's irrelevant.
Edit: Actually, there's this http://www.visual6502.org/JSSim/index.html which may be interesting to you. It is an emulator of the 6502 processor that shows the activation of the electrical circuits on the chip, in parallel to an abstract representation of the processor. But actually, there is at least one intermediate layer that is not represented, and that makes it hard to understand the relation ship between the two layers represented: we're lacking a logic diagram. If you are an experimented CMOS chip designer, you might be able to read the masks directly, but since the layout is optimized for the silicium it's still hard to understand.