| user: | alebal123bal |
| created: | March 25, 2025 |
| karma: | 23 |
| about: | FPGA Engineer experienced in building high-throughput, timing-critical hardware systems using Verilog and VHDL. Strong background in RTL design, deterministic pipelines, and Python-based tooling. Projects span sensor-processing architectures, real-time video pipelines, edge-AI inference, and performance-optimised machine-learning frameworks. |
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